1. Field of the Invention
The present invention relates to the field of integrated circuits, particularly to input/output buffer circuits.
2. Description of Related Art
The development of integrated circuits (ICs) has allowed the electronics industry to establish a trend with products that continue growing increasingly more powerful, reliable, functional, user-friendly, and inexpensive. ICs are widely utilized in a variety of electronic devices, e.g., personal computers, VCRs, wireless phones, pagers, watches, etc., as well as in a host of industrial applications such as heating, air-conditioning, and even automotive control, making these systems more reliable and efficient.
As shown in FIG. 1, an IC package 100 (e.g., a microprocessor) includes a die 102 attached to a metal lead frame 104, which is formed by a framework of lead fingers 106. Die 102 comprises a chip of semiconductor material having an array of active and/or passive microscopic logic elements (not shown) interconnected to form a functioning circuit. Bond wires 108 provide electrical interconnections between input/output (I/O) pads 110, located at the periphery of die 102, and lead fingers 106. Die 102 and lead frame 104 are encased in a ceramic or plastic encapsulant 112 for protection against environmental hazards. Generally, IC package 100 is electrically interconnected with various components located on a printed circuit (PC) board (not shown).
IC chips, such as die 102, are manufactured by simultaneously fabricating a plurality of identical circuits on a thin slice or a flat disk of semiconductor material called a wafer and subsequently separating the wafer into individual chips. Due to the current trend toward miniaturization of electronic components and also to cut manufacturing costs by increasing the number of chips available from a single wafer, it is desirable to make each individual die as small as possible.
FIG. 2 is a schematic view of an IC chip having a conventional I/O-buffer layout. The IC chip or die 102 has a core 114 and a pad ring, located at the periphery of the chip and comprising four adjacent but non-contiguous I/O buffer arrays 116. Each I/O buffer array includes a plurality of I/O pads 110 and a plurality of corresponding I/O buffer circuits 118, electrically coupled to a core logic 120. I/O buffer circuits 118 are linked by a plurality of power rails 121 comprising copper, aluminum, or gold wire traces. The function of power rails 121 is to support the high current-driving capabilities of I/O buffer circuits 118.
A conventional tri-state I/O buffer contains electrostatic discharge (ESD) circuitry activated when core logic 120 uses the corresponding I/O pad for receiving input signals from circuits external to die 102, an output-driver circuitry activated when core logic 120 uses the I/O pad for sending output signals to such external circuits, and circuitry to switch the I/O buffer between input and output modes. The main function of ESD circuitry is to protect core logic 120 from static electricity, since a large static voltage may be inadvertently delivered by people or equipment to a lead (or a pin) of the IC package. The output-driver circuitry is necessary since core logic 120 needs to drive relatively high currents into a PC board having logic elements and wiring with a high capacitance.
Due to the complexity of an I/O buffer circuit, the area it occupies on a die is relatively large. Furthermore, when the design of a die is "pad-limited" (i.e., the size of a chip is determined by the number of I/O pads that are required rather than by the size of the core logic), the pitch (width) of each individual I/O buffer is diminished to approximate the width of an I/O pad. Consequently, I/O buffers must be proportionally elongated to accommodate all the required I/O circuitry, making the pad ring wider and resulting in large unused corner areas 122-128, as shown in FIG. 2. Thus, the conventional layout of I/O buffers in the pad ring uses die area inefficiently, thereby increasing manufacturing costs.